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this is information on a product in full production. march 2012 doc id 022572 rev 1 1/32 1 m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 automotive 16-kbit, 8-kbit, 4-kbit, 2-kbit and 1-kbit (8-bit or 16-bit wide) microwire serial eeprom datasheet ? production data features industry standard microwire tm bus memory array: 1 kb, 2kb, 4kb, 8 kb or 16 kb dual organization: by word (x16) or byte (x8) write ? byte within 5 ms ? word within 5 ms ready/busy signal during programming 2 mhz clock rate sequential read operation single supply voltage: 4.5 v to 5.5 v or 2.5 v to 5.5 v operating temperature range: -40c up to 125c enhanced esd protection more than 1 million write cycles more than 40-year data retention packages ? so8, tssop8 packages: rohs-compliant and halogen-free (ecopack2 ? ) ? pdip8 package: rohs-compliant (ecopack1 ? ) pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width www.st.com
contents m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 2/32 doc id 022572 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 read data from memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 write enable and write disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 erase byte or word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 write all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 ready/busy status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 common i/o operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 contents doc id 022572 rev 1 3/32 13 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of tables m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 4/32 doc id 022572 rev 1 list of tables table 1. memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. instruction set for the m93cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. instruction set for the m93c46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. instruction set for the m93c56 and m93c66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. instruction set for the m93c76 and m93c86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. operating conditions (m93cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. operating conditions (m93cx6-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. ac measurement conditions (m93cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. ac measurement conditions (m93cx6-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. dc characteristics (m93cx6, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. dc characteristics (m93cx6-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. ac characteristics (m93cx6, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. ac characteristics (m93cx6-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 28 table 19. tssop8 ? 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 29 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 list of figures doc id 022572 rev 1 5/32 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. dip, so and tssop connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. read, write, wen, wds sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. erase, eral sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. wral sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. ac testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. synchronous timing (read or write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. synchronous timing (read or write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28 figure 14. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 29
description m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 6/32 doc id 022572 rev 1 1 description the m93c46 (1 kbit), m93c56 (2 kbit), m93c66 (4 kbit), m93c76 (8 kbit) and m93c86 (16 kbit) are electrically erasable prog rammable memory (eeprom) devices accessed through the microwire bus protocol. the memory array can be configured either in bytes (x8b) or in words (x16b). the m93cx6 devices operate within a voltage supply range from 4.5 v to 5.5 v, and the m93cx6-w devices operate within a voltage supply range from 2.5 v to 5.5 v. the m93cx6 devices are guaranteed over the -40c/+125c temperature range and are compliant with the automotive standard aec-q100 grade 1. figure 1. logic diagram table 1. memory size versus organization device number of bits number of 8-bit bytes number of 16-bit words m93c86 16384 2048 1024 m93c76 8192 1024 512 m93c66 4096 512 256 m93c56 2048 256 128 m93c46 1024 128 64 ai01928 d v cc m93cx6 v ss c q s org
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 description doc id 022572 rev 1 7/32 the m93cx6 is accessed by a set of instructions, as summarized in ta bl e 3 , and in more detail in table 4: instruction set for the m93c46 to table 6: instruction set for the m93c76 and m93c86 ). a read data from memory (read) instruction loads the address of the first byte or word to be read in an internal address register. the data at this address is then clocked out serially. the address register is automatically incremented after the data is output and, if chip select input (s) is held high, the m93cx6 can output a sequential stream of data bytes or words. in this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the m93c86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). programming is internally self-timed (the ex ternal clock signal on serial clock (c) may be stopped or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruction. the write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the m93cx6. after the start of the programming cycle, a busy/ready signal is available on serial data output (q) when chip select input (s) is driven high. an internal power-on data protection mechanism in the m93cx6 inhibits the device when the supply is too low. table 2. signal names signal name function direction s chip select input d serial data input input q serial data output output c serial clock input org organization select input v cc supply voltage v ss ground table 3. instruction set for the m93cx6 instruction description data read read data from memory byte or word write write data to memory byte or word wen write enable wds write disable erase erase byte or word byte or word eral erase all memory wral write all memory with same data
description m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 8/32 doc id 022572 rev 1 figure 2. dip, so and tssop connections (top view) 1. see section 12: package mechanical data for package dimensions, and how to identify pin-1. 2. du = don?t use. the du (do not use) pin does not co ntribute to the normal operation of the device. it is reserved for use by stmicroelectroni cs during test sequences. the pin may be left unconnected or may be connected to v cc or v ss . v ss q org du c sv cc d ai01929b m93cx6 1 2 3 4 8 7 6 5
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 connecting to the serial bus doc id 022572 rev 1 9/32 2 connecting to the serial bus figure 3 shows an example of three memory devices connected to an mcu, on a serial bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. the pull-down resistor r (represented in figure 3 ) ensures that no device is selected if the bus master leaves the s line in the high impedance state. in applications where the bus master may be in a state where all inputs/outputs are high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled low): this ensures that c does not become high at the same time as s goes low, and so, that the t slch requirement is met. the ty pical value of r is 100 k . figure 3. bus master and memory devices on the serial bus ai14377b bus master m93xxx memory device sdo sdi sck cqd s m93xxx memory device cqd s m93xxx memory device cqd s cs3 cs2 cs1 org org org rr r v cc v cc v cc v cc v ss v ss v ss v ss r
operating features m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 10/32 doc id 022572 rev 1 3 operating features 3.1 supply voltage (v cc ) 3.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied. in order to secure a stable dc supply voltage, it is reco mmended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 3.1.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s) line is not allowed to float and should be driven to v ss , it is therefore recommended to connect the s line to v ss via a suitable pull-down resistor. the v cc rise time must not vary faster than 1 v/s. 3.1.3 power-up and device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in operating conditions, in section 11: dc and ac parameters ). when v cc passes the por threshold, the device is reset and is in the following state: standby power mode deselected (assuming that there is a pull-down resistor on the s line) 3.1.4 power-down at power-down (continuous decrease in v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in the standby power mode (that is, there should be no internal write cycle in progress).
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 memory organization doc id 022572 rev 1 11/32 4 memory organization the m93cx6 memory is organized either as by tes (x8) or as words (x16). if organization select (org) is left unconnected (or connected to v cc ) the x16 organization is selected; when organization select (org) is connected to ground (v ss ) the x8 organization is selected. when the m93cx6 is in standby mode, organization select (org) should be set either to v ss or v cc for minimum power consumption. any voltage between v ss and v cc applied to organization select (org) may increase the standby current.
instructions m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 12/32 doc id 022572 rev 1 5 instructions the instruction set of the m93cx6 devices contains seven instructions, as summarized in ta bl e 4 to ta b l e 6 . each instruction consists of the following parts, as shown in figure 4: read, write, wen, wds sequences : each instruction is preceded by a rising edge on chip select input (s) with serial clock (c) being held low. a start bit, which is the first ?1? read on serial data input (d) during the rising edge of serial clock (c). two op-code bits, read on serial data input (d) during the rising edge of serial clock (c). (some instructions also use the first two bits of the address to define the op-code). the address bits of the byte or word that is to be accessed. for the m93c46, the address is made up of 6 bits for the x16 orga nization or 7 bits for the x8 organization (see ta bl e 4 ). for the m93c56 and m93c66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see ta bl e 5 ). for the m93c76 and m93c86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see ta bl e 6 ). the m93cx6 devices are fabricated in cmos technology and are therefore able to run as slow as 0 hz (static input signals) or as fast as the maximum ratings specified in ?ac characteristics? tables, in section 11: dc and ac parameters . table 4. instruction set for the m93c46 instruction description start bit op- code x8 origination (org = 0) x 16 origination (org = 1) address (1) data required clock cycles address (1) data required clock cycles read read data from memory 1 10 a6-a0 q7-q0 a5-a0 q15-q0 write write data to memory 1 01 a6-a0 d7-d0 18 a5-a0 d15-d0 25 wen write enable 1 00 11x xxxx 10 11 xxxx 9 wds write disable 1 00 00x xxxx 10 00 xxxx 9 erase erase byte or word 1 11 a6-a0 10 a5-a0 9 eral erase all memory 1 00 10x xxxx 10 10 xxxx 9 wral write all memory with same data 100 01x xxxx d7-d0 18 01 xxxx d15-d0 25 1. x = don't care bit.
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 instructions doc id 022572 rev 1 13/32 table 5. instruction set for the m93c56 and m93c66 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1) (2) data required clock cycles address (1) (3) data required clock cycles read read data from memory 1 10 a8-a0 q7-q0 a7-a0 q15-q0 write write data to memory 1 01 a8-a0 d7-d0 20 a7-a0 d15-d0 27 wen write enable 1 00 1 1xxx xxxx 12 11xx xxxx 11 wds write disable 1 00 0 0xxx xxxx 12 00xx xxxx 11 erase erase byte or word 1 11 a8-a0 12 a7-a0 11 eral erase all memory 100 1 0xxx xxxx 12 10xx xxxx 11 wral write all memory with same data 100 0 1xxx xxxx d7-d0 20 01xx xxxx d15-d0 27 1. x = don't care bit. 2. address bit a8 is not decoded by the m93c56. 3. address bit a7 is not decoded by the m93c56. table 6. instruction set for the m93c76 and m93c86 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1), (2) data required clock cycles address (1) (3) data required clock cycles read read data from memory 1 10 a10-a0 q7-q0 a9-a0 q15-q0 write write data to memory 1 01 a10-a0 d7-d0 22 a9-a0 d15-d0 29 wen write enable 1 00 11x xxxx xxxx 14 11 xxxx xxxx 13 wds write disable 1 00 00x xxxx xxxx 14 00 xxxx xxxx 13 erase erase byte or word 1 11 a10-a0 14 a9-a0 13 eral erase all memory 1 00 10x xxxx xxxx 14 10 xxxx xxxx 13 wral write all memory with same data 100 01x xxxx xxxx d7-d0 22 01 xxxx xxxx d15-d0 29 1. x = don't care bit. 2. address bit a10 is not decoded by the m93c76. 3. address bit a9 is not decoded by the m93c76.
instructions m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 14/32 doc id 022572 rev 1 5.1 read data from memory the read data from memory (read) instruction outputs data on serial data output (q). when the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. a dummy 0 bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. output data changes are triggered by the rising edge of serial clock (c). the m93cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the chip select input (s) is held high. in this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. 5.2 write enable and write disable the write enable (wen) instruction enables the future execution of erase or write instructions, and the write disable (wds) instruction disables it. when power is first applied, the m93cx6 init ializes itself so that erase and wr ite instructions are disabled. after an write enable (wen) instruction has been executed, erasing and writing remains enabled until an write disable (wds) inst ruction is executed, or until v cc falls below the power-on reset threshold voltage. to protect the memory contents from accidental corruption, it is advisable to issue the write disable (wds) in struction after every write cycle. the read data from memory (read) instruction is not af fected by the write enable (wen) or write disable (wds) instructions.
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 instructions doc id 022572 rev 1 15/32 figure 4. read, write, wen, wds sequences 1. for the meanings of an, xn, qn and dn, see table 4 , table 5 and table 6 . 5.3 erase byte or word the erase byte or word (erase) instruction sets the bits of the addressed me mory byte (or word) to 1. once the addre ss has been correctly decoded, the falling edge of the chip select input (s) starts the self-timed erase cycle. the completion of the cycle can be detected by monitoring the ready/busy line, as described in section 6: ready/busy status . ai00878d 1 1 0 an a0 qn q0 data out d s q read s write addr op code 1 0an a0 data in d q op code dn d0 1 busy ready s write enable 1 0xnx0 d op code 1 01 s write disable 1 0xnx0 d op code 0 0 0 check status addr
instructions m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 16/32 doc id 022572 rev 1 5.4 write for the write data to memory (write) instruction, 8 or 16 data bits follow the op-code and address bits. these form the byte or word that is to be written. as with the other bits, serial data input (d) is sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be pr ogrammed. the comple tion of the cycle can be detected by monitoring the ready/busy line, as described later in this document. once the write cycle has been started, it is internally self-timed (the external clock signal on serial clock (c) may be stopped or left running after the start of a write cycle). the cycle is automatically preceded by an erase cycle, so it is unnecessary to execute an explicit erase instruction before a write data to memory (write) instruction. figure 5. erase, eral sequences 1. for the meanings of an and xn, please see table 4 , table 5 and table 6 . 5.5 erase all the erase all memory (eral) instruction erases the whole memory (all memory bits are set to 1). the format of the instruction requires that a dummy address be provided. the erase cycle is conducted in the same way as the erase instruction (erase). the completion of the cycle can be detected by monitoring the ready/busy line, as described in section 6: ready/busy status . ai00879b s erase 1 1 d q addr op code 1 busy ready check status s erase all 1 0 d q op code 1 busy ready check status 0 0 an a0 xn x0 addr
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 instructions doc id 022572 rev 1 17/32 5.6 write all as with the erase all memory (eral) instruct ion, the format of the write all memory with same data (wral) instruction requires that a dummy address be provided. as with the write data to memory (write) instruction, the format of th e write all memory with same data (wral) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. this value is written to all the addresses of the memory device. the completion of the cycle can be detected by monitoring the ready/busy line, as described next. figure 6. wral sequence 1. for the meanings of xn and dn, please see table 4 , table 5 and table 6 . ai00880c s write all data in d q addr op code dn d0 busy ready check status 1 0 0 0 1 xn x0
ready/busy status m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 18/32 doc id 022572 rev 1 6 ready/busy status while the write or erase cycle is underwa y, for a write, erase, wral or eral instruction, the busy signal (q=0) is returned w henever chip select inpu t (s) is driven high. (please note, though, that there is an initial delay, of t slsh , before this status information becomes available). in this state, the m93cx6 ignores any data on the bus. when the write cycle is completed, and chip select input (s) is driven high, the ready signal (q=1) indicates that the m93cx6 is ready to receive the next instruction. serial data output (q) remains set to 1 until the chip select input (s) is brought lo w or until a new start bit is decoded. 7 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 8 common i/o operation serial data output (q) and serial data input (d) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (a0) clashes with the first data bit on serial data output (q). please see the application note an394 for details.
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 clock pulse counter doc id 022572 rev 1 19/32 9 clock pulse counter in a noisy environment, the number of pulses received on serial clock (c) may be greater than the number delivered by the master (the microcontroller). this can lead to a misalignment of the instruction of one or more bits (as shown in figure 7 ) and may lead to the writing of erroneous data at an erroneous address. to avoid this problem, the m93cx6 has an on-c hip counter that counts the clock pulses from the start bit until the falling edge of the chip select input (s). if the number of clock pulses received is not the number expected, the write, erase, eral or wral instruction is aborted, and the contents of the memory are not modified. the number of clock cycles expected for each instruction, and for each member of the m93cx6 family, are summarized in table 4: instruction set for the m93c46 to ta bl e 6 : instruction set for the m93c76 and m93c86 . for example, a write data to memory (write) instruction on the m93c56 (or m93c66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of chip select input (s). that is: 1 start bit + 2 op-code bits + 9 address bits + 8 data bits figure 7. write sequence with one clock glitch ai01395 s an-1 c d write start d0 "1" "0" an glitch an-2 address and data are shifted by one bit
maximum rating m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 20/32 doc id 022572 rev 1 10 maximum rating stressing the device outside the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering pdip 260 (1) 1. t lead max must not be applied for more than 10 s. other packages see note (2) 2. compliant with jedec std j-std-020 (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c v out output range (q = v oh or hi-z) ?0.50 v cc +0.5 v v in input range ?0.50 v cc +1 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (3) 3. positive and negative pulses appli ed on pin pairs, according to the aec-q100-002 (compliant with jedec std jesd22-a114, c1 = 100pf, r1 = 1500 , r2 = 500 ). 4000 v
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 dc and ac parameters doc id 022572 rev 1 21/32 11 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 8. operating conditions (m93cx6) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature ?40 125 c table 9. operating conditions (m93cx6-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 125 c table 10. ac measurement conditions (m93cx6) symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input voltage levels 0.4 v to 2.4 v v input timing reference voltages 1.0 v and 2.0 v v output timing reference voltages 0.8 v and 2.0 v v table 11. ac measurement conditions (m93cx6-w) symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input voltage levels 0.2 v cc to 0.8 v cc v input timing reference voltages 0.3 v cc to 0.7 v cc v output timing reference voltages 0.3 v cc to 0.7 v cc v
dc and ac parameters m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 22/32 doc id 022572 rev 1 figure 8. ac testing input output waveforms table 12. capacitance symbol parameter test condition (1) 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 1 mhz. min max unit c out output capacitance v out = 0v 5 pf c in input capacitance v in = 0v 5 pf table 13. dc characteristics (m93cx6, device grade 3) symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current v cc = 5 v, s = v ih , f = 2 mhz, q = open 2 ma i cc1 supply current (standby) v cc = 5 v, s = v ss , c = v ss , org = v ss or v cc , pin7 = v cc , v ss or hi-z 15 a v il (1) 1. please note that the input and output levels defined in this table are compatible with ttl logic levels and are not fully compatible with cmos levels (as defined in table 14 ). input low voltage v cc = 5 v 10% ?0.45 0.8 v v ih (1) input high voltage v cc = 5 v 10% 2 v cc + 1 v v ol (1) output low voltage v cc = 5 v, i ol = 2.1 ma 0.4 v v oh (1) output high voltage v cc = 5 v, i oh = ?400 a 0.8 v cc v -36 2.4v 0.4v 6 0.8v 2v 1v )nput 0.8v cc 0.2v cc 0.7v cc 0.3v cc m93cxx /utput )nputvoltagelevels )nputandoutput timingreferencelevels )nputvoltagelevels -#88 7
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 dc and ac parameters doc id 022572 rev 1 23/32 table 14. dc characteristics (m93cx6-w, device grade 3) symbol parameter test co ndition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5 v, s = v ih , f = 2 mhz, q = open 2 ma v cc = 2.5 v, s = v ih , f = 2 mhz, q = open 1 ma i cc1 supply current (standby) v cc = 2.5 v, s = v ss , c = v ss , org = v ss or v cc , pin7 = v cc , v ss or hi-z 5 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5 v, i ol = 2.1 ma 0.4 v v cc = 2.5 v, i ol = 100 a 0.2 v v oh output high voltage (q) v cc = 5 v, i oh = ?400 a 0.8 v cc v v cc = 2.5 v, i oh = ?100 a v cc ?0.2 v
dc and ac parameters m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 24/32 doc id 022572 rev 1 table 15. ac characteristics (m93cx6, device grade 3) test conditions specified in table 8 and table 10 symbol alt. parameter min. max. unit f c f sk clock frequency d.c. 2 mhz t slch chip select low to clock high 50 ns t shch t css chip select setup time m93c46, m93c56, m93c66 50 ns chip select setup time m93c76, m93c86 50 ns t slsh (1) 1. chip select input (s) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 200 ns t chcl (2) 2. t chcl + t clch 1 / f c . t skh clock high time 200 ns t clch (2) t skl clock low time 200 ns t dvch t dis data in setup time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock setup time (relative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase or write cycle time 5 ms
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 dc and ac parameters doc id 022572 rev 1 25/32 table 16. ac characteristics (m93cx6-w, device grade 3) test conditions specified in table 9 and table 11 symbol alt. parameter min. max. unit f c f sk clock frequency d.c. 2 mhz t slch chip select low to clock high 50 ns t shch t css chip select set-up time 50 ns t slsh (1) 1. chip select input (s) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 200 ns t chcl (2) 2. t chcl + t clch 1 / f c . t skh clock high time 200 ns t clch (2) t skl clock low time 200 ns t dvch t dis data in set-up time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock set-up time (relative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase or write cycle time 5 ms
dc and ac parameters m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 26/32 doc id 022572 rev 1 figure 9. synchronous timing (start and op-code input) figure 10. synchronous timing (read or write) figure 11. synchronous timing (read or write) ai01428 c op code op code start s d op code input start tdvch tshch tclsh tchcl tclch tchdx ai00820c c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15/q7 q0 ai01429 c d q address/data input hi-z tdvch tslch a0/d0 s write cycle tslsh tchdx an tclsl tslqz busy tshqv tw ready
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 package mechanical data doc id 022572 rev 1 27/32 12 package mechanical data in order to meet environmental requirements, st offers the m93cxx devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com . figure 12. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package outline 1. drawing is not to scale. table 17. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 5.33 0.2098 a1 0.38 0.015 a2 3.3 2.92 4.95 0.1299 0.115 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.022 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.2 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.365 0.3551 0.4 e 7.87 7.62 8.26 0.3098 0.3 0.3252 e1 6.35 6.1 7.11 0.25 0.2402 0.2799 e 2.54 - - 0.1 - - ea 7.62 - - 0.3 - - eb 10.92 0.4299 l 3.3 2.92 3.81 0.1299 0.115 0.15 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
package mechanical data m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 28/32 doc id 022572 rev 1 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 18. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.75 0.0689 a1 0.1 0.25 0.0039 0.0098 a2 1.25 0.0492 b 0.28 0.48 0.011 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.1 0.0039 d 4.9 4.8 5 0.1929 0.189 0.1969 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h 0.25 0.5 0.0098 0.0197 k 08 08 l 0.4 1.27 0.0157 0.05 l1 1.04 0.0409 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 package mechanical data doc id 022572 rev 1 29/32 figure 14. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 19. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 1.2 0.0472 a1 0.05 0.15 0.002 0.0059 a2 1 0.8 1.05 0.0394 0.0315 0.0413 b 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 cp 0.1 0.0039 d 3 2.9 3.1 0.1181 0.1142 0.122 e 0.65 - - 0.0256 - - e 6.4 6.2 6.6 0.252 0.2441 0.2598 e1 4.4 4.3 4.5 0.1732 0.1693 0.1772 l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 0.0394 0 8 0 8 n (pin number) 8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 30/32 doc id 022572 rev 1 13 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 20. ordering information scheme example: m93c86 ? w mn 3 t p /s device type m93 = microwire serial eeprom device function 86 = 16 kbit (2048 x 8) 76 = 8 kbit (1024 x 8) 66 = 4 kbit (512 x 8) 56 = 2 kbit (256 x 8) 46 = 1 kbit (128 x 8) operating voltage blank = v cc = 4.5 to 5.5 v w = v cc = 2.5 to 5.5 v package bn = pdip8 mn = so8 (150 mils width) dw = tssop8 (169 mils width) device grade 3 = device tested with high reliability certified flow. automotive temperature range (?40 to 125 c) packing blank = standard packing t = tape and reel packing plating technology p or g = ecopack ? (rohs compliant) process /s = manufacturing technology code
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 revision history doc id 022572 rev 1 31/32 14 revision history table 21. document revision history date revision changes 14-mar-2012 1 init ial release.
m93c86-125 M93C76-125 m93c66-125 m93c56-125 m93c46-125 32/32 doc id 022572 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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